1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device, which has a memory array consisting of non-volatile memory cells arranged in rows and columns and having a stacked gate structure, and more particularly to a writing control circuit for controlling a writing transistor used to writing data into the memory cells.
2. Description of the Related Art
EPROMs (Erasable Programmable Read Only Memories) and EEPROMs (Electrical Erasable Programmable Read Only Memories) each employ MOS transistors having a stacked gate structure and serving as memory cells. Writing data into the memory cells is performed by injecting hot electrons from the drain of the cell into the floating gate thereof. An EPROM with Tunnel Oxide called an "ETOX" (a trademark of the US company of Intel Corporation) type cell is one of such EPROM cells.
A non-volatile memory cell of this type generally has a structure as shown in FIG. 1. As is shown in the figure, second conductivity-type source and drain regions 72 and 73 are formed separate from each other in a major surface portion of a first conductivity-type semiconductor substrate 71. A first gate insulation film (tunnel insulation film) 74 is formed on the substrate 71 between the source and drain regions 72 and 73. A floating gate 75, a second gate insulation film 77, and a control gate 76 are formed on the first gate insulation 74 in the order mentioned.
At the time of writing data into the memory cell (i.e., at the time of programming), a low voltage (e.g. of 0 V) is applied to the cell as the source voltage VS and substrate potential, while a high voltage Vpp for writing is applied to the same as the control gate voltage VCG and drain voltage VD. The high voltage Vpp is supplied from the outside of the memory device, or alternatively a voltage, obtained by increasing a power supply voltage for the memory device in the same, is used as the high voltage Vpp. As a result, an on-current flows between the drain and source, giving rise to pairs of hot electrons and hot holes in the vicinity of the drain region 73. The hot holes flow through the substrate 71 as a substrate current, while the hot electrons are injected into the floating gate 75 via the first insulation film 74. Thus, the threshold voltage of the transistor is increased, which is termination of writing.
In a case where the memory cell is an ETOX type cell, erasion of data is performed by supplying the high voltage Vpp and low voltage (0 V) as the source voltage VS and control gate voltage VCG, respectively, and causing the drain region 73 to be in a floating state. In this case, the potential VFG of the floating gate 75 is determined based on the ratio of the capacity between the control gate 76 and floating gate 75 to the capacity between the floating gate 75 and source region 72 is determined, and on the source voltage VS. Application of the above-described voltages causes a Fowler-Nordheim tunnel current to flow between the source region 72 and floating gate 75, thus eliminating the electrons from the floating gate 75 and terminating erasion (i.e., the threshold voltage returns to a value having assumed before writing).
In the memory cell array consisting of the above-described memory cells arranged in rows and columns, there exist a plurality of non-selected memory cells, which are connected to each selected memory cell by means of a corresponding common bit or word line. These non-selected memory cells may cause the following problems at the time of writing:
To write data into a selected memory cell, the drain and gate of each of non-selected memory cells which are connected to the selected memory cell via a common bit line are supplied with the high voltage Vpp and a ground potential Vss, respectively. At this time, an intense electric field is caused between the drain and floating gate of the non-selected cell. In particular, where the non-selected cell is in its writing state, and hence electrons are accumulated at the floating gate, the electric field between the drain and floating gate may be highly concentrated, resulting in a breakdown in a junction between the drain region and substrate, or the electrons at the floating gate may flow into the drain region through the tunnel insulation film. This being so, the reliability of the memory cell may be reduced. Thus, it is necessary, at the time of writing, to keep the drain voltage at a low level enough to obtain satisfactory writing characteristics without reducing the reliability of the memory cell.
Further, with the development of the refining technique for semiconductor devices, it has been necessary to reduce the thickness of a gate insulation film and to increase the concentration of an impurity contained in a channel region. This may cause a reduction in the breakdown voltage of a pn-junction or an increase in an electric field applied onto the gate insulation film. The finer the device, the more important to reliably and accurately control the upper limit of the drain voltage at the time of writing.
FIG. 2 is a schematic equivalent circuit diagram, useful in explaining a writing system employed in an EPROM or EEPROM, and showing a memory cell 81, a column-selecting transistor 84, a writing transistor 85, and a write control circuit 90. The memory cell 81 has its control gate connected to a word line 82, its drain connected to a bit line 83, and its source connected to a ground terminal Vss. An end of the bit lien 83 is connected to an end of the current path of the column-selecting transistor 84. The transistor 84 is of the n-channel enhancement type. The current path of the writing transistor 85 is connected between the other end of the current path of the transistor 84 and a power supply SW in the memory. The transistor 85 is of the n-channel enhancement type. The power supply SW supplies a high voltage Vpp (e.g., 12.5 V) at the time of writing data into the memory cell. The gate of the writing transistor 85 is connected to a write control circuit 90. The word line 82 and the gate of the column-selecting transistor 84 are connected to the output terminals of a row decoder and a column decoder (not shown), respectively. In accordance with the output of the row decoder, the high voltage Vpp is applied to the word line 82 when the line is selected, and the ground potential Vss when it is not selected. Further, in accordance with the output of the column decoder, the high voltage Vpp is applied to the gate of the column-selecting transistor 84 when the transistor is selected, and the ground potential Vss when it is not selected. A write control voltage VA or the ground potential Vss is applied to the gate of the writing transistor 85 in accordance with whether write input data from the write control circuit 90 is at "H" level or "L" level. The "H" level of the bit line 83 is VA-V.sub.THN (V.sub.THN represents the threshold voltage of the n-channel enhancement-type transistor 85), so that the drain voltage of the memory cell 81 is determined by the write control voltage VA.
FIG. 3 is a circuit diagram, showing a circuit for generating the write control voltage VA, which is provided in the write control circuit 90 shown in FIG. 2. The circuit 90 comprises an n-channel enhancement-type transistor 91, a p-channel enhancement-type transistor 92, and an n-channel depletion-type transistor 93. The current paths of the transistors 91 to 93 are connected in series to one another between the high voltage power supply Vpp and ground terminal Vss. In the transistor 91, the gate is connected to the drain. In the transistor 92, the gate is connected to a power supply Vcc, and the back gate is connected to the source. Further, in the transistor 93, the gate is connected to the source. The conductance gm of the transistor 93 is set smaller than that of the transistor 91. Thus, when the write data is at "H" level, the write control voltage VA=Vpp-V.sub.THN (V.sub.THN represents the threshold voltage of the transistor 91) is output from the source of the transistor 91. Accordingly, the "H" level of the bit line 83 is VA-V.sub.THN =Vpp-2V.sub.THN.
In the above-described structure, however, the write control voltage VA is created by reducing the high voltage Vpp by the threshold voltage V.sub.THN of the transistor 91, so that the degree of dependence of the write control voltage VA upon Vpp and V.sub.THN is high, which may cause the upper limit of the drain voltage of the memory cell to be unstable. In particular, the threshold voltage V.sub.THN is assumed when the transistor 91 receives a substrate bias of not less than 5 V, and is as much as 2 V or more. In addition, the transistor 91 is greatly influenced by the substrate bias, and highly depends upon the dose of impurity ions used at the time of channel ion implantation for controlling the threshold voltage. As a result, the threshold voltage V.sub.THN greatly varies, and hence it is difficult to accurately control the upper limit of the drain voltage of the memory cell at the time of writing data into the cell.